Non-volatile memory devices are popular in contemporary electronic systems, especially portable electronic systems that rely on battery sources for power. Such non-volatile memory devices retain information even when the system power source is inactivated, and therefore do not require a power-consuming refresh operation for maintaining stored data.
With reference to FIG. 1, in a conventional non-volatile memory cell structure of the SONOS type, a charge trapping structure 110 is formed on a silicon substrate 102 where a drain region 104 and a source region 106 are separated from each other by a predetermined distance. The charge trapping structure 110 has a stacked structure, in which a tunneling layer 112 formed of a first silicon oxide layer, a charge trapping layer 114 formed of a silicon nitride layer, and a blocking layer 116 formed of a second silicon oxide layer are sequentially stacked on a surface of the silicon substrate 102. A control gate electrode 120, which is formed of a polysilicon layer, is formed on the charge trapping structure 110.
To perform a programming or writing operation, a positive bias voltage is applied to the gate electrode 120 and the source region 106, and the drain region 104 is grounded. The voltage that is applied to the gate electrode 120 and the source region 106 induces a vertical electric field and a horizontal electric field along the channel region in a direction from the drain region 104 to the source region 106. Due to the electric fields, electrons are pushed away from the drain region 104 and accelerate toward the source region 106. The electrons gain energy when moving along the channel region, and some electrons enter into a hot state whereby they can gain enough energy to enter the charge trapping layer 114, leaping over the potential barrier of the tunneling layer 112. This happens most frequently near the drain region 106, because the electrons can gain the greatest amount of energy in that region. Once the electrons in the hot state enter the charge trapping layer 114, the electrons in the hot state are trapped in the charge trapping layer 114 and become stored therein, and thus the threshold voltage of the memory cell increases.
To perform an erasing operation, a different voltage than the voltage used in programming or reading the memory cell is required. For example, a positive bias voltage is applied to the source region 106, and a negative bias voltage is applied to the gate electrode 120. The drain region 104 is floated. In this state, the electrons, which are stored in the charge trapping layer 114, move toward the source region 106, and holes within the source region 106 migrate to the charge trapping layer 114. The electrons stored in the charge trapping layer 114 are removed or neutralized by the holes, and thus data on the memory cell is erased.
In a conventional SONOS memory device, a certain amount of electrons that were previously trapped in the overlapping region of a gate electrode and a source region or that of a gate electrode and a drain region may still remain in the charge trapping layer following completion of the erasing operation.
The potential barrier between a channel region and a source/drain region may increase due to the remaining electrons following the erasing operation. As the potential barrier increases, the sub-threshold voltage slope of the non-volatile memory device declines. This phenomenon is described in the article “Characterization of Channel Hot Electron Injection by the Subthreshold Slope of NROM™ Device” by Eli Lusky et al., IEEE Electron Device Letters, Vol. 22, No. 11, November 2001.
Device characteristics are degraded when this occurs because the difference in the threshold voltage between the programmed state and the erased state of the device is decreased.